// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
/*
 * Copyright (c) 2023 panzhijian@allwinnertech.com
 */

#ifndef _DT_BINDINGS_RESET_SUN55IW6_H_
#define _DT_BINDINGS_RESET_SUN55IW6_H_

#define RST_BUS_ITS0		0
#define RST_BUS_NSI		1
#define RST_BUS_NSI_CFG		2
#define RST_BUS_DMA0		3
#define RST_BUS_DMA1		4
#define RST_BUS_SPINLOCK	5
#define RST_BUS_MSGBOX0		6
#define RST_BUS_MSGBOX_CORE0	7
#define RST_BUS_MSGBOX_CORE1	8
#define RST_BUS_MSGBOX_CORE2	9
#define RST_BUS_MSGBOX_CORE3	10
#define RST_BUS_MSGBOX_RV	11
#define RST_BUS_PWM0		12
#define RST_BUS_PWM1		13
#define RST_BUS_PWM2		14
#define RST_BUS_DBGSY		15
#define RST_BUS_SYSDAP		16
#define RST_BUS_TIME		17
#define RST_BUS_TIMER_RV	18
#define RST_BUS_DE0		19
#define RST_BUS_G2D		20
#define RST_BUS_DE_SY		21
#define RST_BUS_VE		22
#define RST_BUS_CE_SY		23
#define RST_BUS_CE		24
#define RST_BUS_NPU_GLB		25
#define RST_BUS_NPU_AHB		26
#define RST_BUS_NPU_AXI		27
#define RST_BUS_NPU_CORE	28
#define RST_BUS_RV_SY		29
#define RST_BUS_RV_CORE		30
#define RST_BUS_RV_CFG		31
#define RST_BUS_DRAM		32
#define RST_BUS_NAND0		33
#define RST_BUS_SMHC0		34
#define RST_BUS_SMHC1		35
#define RST_BUS_SMHC2		36
#define RST_BUS_UART0		37
#define RST_BUS_UART1		38
#define RST_BUS_UART2		39
#define RST_BUS_UART3		40
#define RST_BUS_UART4		41
#define RST_BUS_UART5		42
#define RST_BUS_UART6		43
#define RST_BUS_UART7		44
#define RST_BUS_UART8		45
#define RST_BUS_UART9		46
#define RST_BUS_UART10		47
#define RST_BUS_UART11		48
#define RST_BUS_UART12		49
#define RST_BUS_UART13		50
#define RST_BUS_UART14		51
#define RST_BUS_TWI0		52
#define RST_BUS_TWI1		53
#define RST_BUS_TWI2		54
#define RST_BUS_TWI3		55
#define RST_BUS_TWI4		56
#define RST_BUS_TWI5		57
#define RST_BUS_TWI6		58
#define RST_BUS_SPI0		59
#define RST_BUS_SPI1		60
#define RST_BUS_SPI2		61
#define RST_BUS_SPIF		62
#define RST_BUS_SPI3		63
#define RST_BUS_SPI4		64
#define RST_BUS_GPADC0		70
#define RST_BUS_GPADC1		71
#define RST_BUS_GPADC2		72
#define RST_BUS_GPADC3		73
#define RST_BUS_TH		74
#define RST_BUS_IRRX0		75
#define RST_BUS_IRTX		76
#define RST_BUS_LRADC		77
#define RST_BUS_TPADC		78
#define RST_BUS_LBC		79
#define RST_BUS_IRRX1		80
#define RST_BUS_IRRX2		81
#define RST_BUS_IRRX3		82
#define RST_BUS_I2SPCM0		83
#define RST_BUS_I2SPCM1		84
#define RST_BUS_I2SPCM2		85
#define RST_BUS_I2SPCM3		86
#define RST_BUS_OWA		87
#define RST_BUS_DMIC		88
#define RST_BUS_AUDIO_CODEC	89
#define RST_USB_PHY0_RSTN	90
#define RST_USB_20_0_DEVICE	91
#define RST_USB_20_0_HOST_EHCI	92
#define RST_USB_20_0_HOST_OHCI	93
#define RST_USB_PHY1_RSTN	94
#define RST_USB_20_1_HOST_EHCI	95
#define RST_USB_20_1_HOST_OHCI	96
#define RST_USB_30		97
#define RST_BUS_PCIE		98
#define RST_BUS_PCIE_PWRUP	99
#define RST_BUS_SERDES_NOPPU	100
#define RST_BUS_SERDE		101
#define RST_BUS_GMAC0_AXI	102
#define RST_BUS_GMAC0		103
#define RST_BUS_GMAC1_AXI	104
#define RST_BUS_GMAC1		105
#define RST_BUS_VO0_TCONLCD0	106
#define RST_BUS_LVDS0		107
#define RST_BUS_DSI0		108
#define RST_BUS_DP		109
#define RST_BUS_VIDEO_OUT0	110
#define RST_BUS_LEDC		111
#define RST_BUS_CSI		112
#define RST_BUS_ISP		113

#endif /* _DT_BINDINGS_RESET_SUN55IW6_H_ */
